Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 35

Figure 16.12 Slave Receive Mode Operation Timing 2..............................................................728
Figure 16.13 Block Diagram of Noise Conceler.........................................................................729
Figure 16.14 Sample Flowchart for Master Transmit Mode.......................................................730
Figure 16.15 Sample Flowchart for Master Receive Mode ........................................................731
Figure 16.16 Sample Flowchart for Slave Transmit Mode .........................................................732
Figure 16.17 Sample Flowchart for Slave Receive Mode...........................................................733
Figure 16.18 Timing of the Bit Synchronous Circuit..................................................................735
Section 17 A/D Converter
Figure 17.1 Block Diagram of A/D Converter............................................................................738
Figure 17.2 A/D Conversion Timing ..........................................................................................745
Figure 17.3 External Trigger Input Timing.................................................................................746
Figure 17.4 A/D Conversion Precision Definitions ....................................................................748
Figure 17.5 A/D Conversion Precision Definitions ....................................................................748
Figure 17.6 Example of Analog Input Circuit.............................................................................749
Figure 17.7 Example of Analog Input Protection Circuit ...........................................................751
Figure 17.8 Analog Input Pin Equivalent Circuit........................................................................751
Section 18 D/A Converter
Figure 18.1 Block Diagram of D/A Converter............................................................................753
Figure 18.2 Example of D/A Converter Operation .....................................................................761
Section 20 Flash Memory (F-ZTAT Version)
Figure 20.1 Block Diagram of Flash Memory ...........................................................................766
Figure 20.2 Flash Memory State Transitions ..............................................................................767
Figure 20.3 Boot Mode ...............................................................................................................768
Figure 20.4 User Program Mode.................................................................................................769
Figure 20.5 384-Kbyte Flash Memory Block Configuration (Modes 3, 4, and 7) ......................771
Figure 20.6 Programming/Erasing Flowchart Example in User Program Mode ........................781
Figure 20.7 Flowchart for Flash Memory Emulation in RAM ...................................................782
Figure 20.8 Example of RAM Overlap Operation ......................................................................783
Figure 20.9 Program/Program-Verify Flowchart........................................................................785
Figure 20.10 Erase/Erase-Verify Flowchart................................................................................787
Figure 20.11 Power-On/Off Timing (H8S/2378R Series) ..........................................................791
Figure 20.12 Mode Transition Timing (Example: Boot Mode → User Mode ↔
User Program Mode)...............................................................................................792
Section 21 Clock Pulse Generator
Figure 21.1 Block Diagram of Clock Pulse Generator ...............................................................793
Figure 21.2 Connection of Crystal Oscillator (Example)............................................................796
Figure 21.3 Crystal Oscillator Equivalent Circuit.......................................................................796
Figure 21.4 External Clock Input (Examples) ............................................................................797
Figure 21.5 External Clock Input Timing ...................................................................................798
Figure 21.6 Note on Oscillator Board Design.............................................................................800
Figure 21.7 Recommended External Circuitry for PLL Circuit..................................................800
Section 22 Power-Down Modes
Figure 22.1 Mode Transitions .....................................................................................................803
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