Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 241

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SDRAM
Address bus
Precharge-sel
Read
CKE
DQMU, DQML
Data bus
Write
CKE
DQMU, DQML
Data bus
RAS Down Mode: Even when burst operation is selected, it may happen that access to continuous
synchronous DRAM space is not continuous, but is interrupted by access to another space. In this
case, if the row address active state is held during the access to the other space, the read or write
command can be issued without ACTV command generation similarly to DRAM RAS down
mode.
To select RAS down mode, set the BE bit to 1 in DRAMCR regardless of the RCDM bit settings.
The operation corresponding to DRAM RAS up mode is not supported by this LSI.
Figure 6.53 shows an example of the timing in RAS down mode.
T T
p r
Column
Row address
address 1
Row address
PALL ACTV READ
PALL ACTV NOP
Figure 6.52 Operation Timing of Burst Access
(BE = 1, SDWCD = 0, CAS Latency 2)
T T T
c1 cl c2
Column address
High
NOP
High
WRIT
T T
c1 cl
Column address 2
READ NOP
NOP WRIT
Rev. 1.0, 09/01, page 197 of 904
T
c2
NOP