Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 527

Bit Bit Name
7 —
6 PG6DDR
5 PG5DDR
4 PG4DDR
3 PG3DDR
2 PG2DDR
1 PG1DDR
0 PG0DDR
Notes: 1. PG0DDR is initialized to 1 in modes 1, 2, 5, and 6, and to 0 in modes 4 and 7.
Initial Value R/W
0 —
0 W
0 W
0 W
0 W
0 W
0 W
1/0* W
Description
Reserved
•
Modes 1, 2, 4, 5, and 6
Pins PG6 to PG4 function as bus control input/output
pins (%5(42, %$&., and %5(4) when the
appropriate bus controller settings are made.
Otherwise, these pins are I/O ports, and their
functions can be switched with PGDDR.
When the &6 output enable bits (CS3E to CS0E) are
set to 1, pins PG3 to PG0 function as &6 output pins
when the corresponding PGDDR bit is set to 1, and
as input ports when the bit is cleared to 0. When
CS3E to CS0E are cleared to 0, pins PG3 to PG0 are
I/O ports, and their functions can be switched with
PGDDR.
•
Mode 7 (when EXPE = 1)
Pins PG6 to PG4 function as bus control input/output
pins (%5(42, %$&., and %5(4) when the
appropriate bus controller settings are made.
Otherwise, these pins are output ports when the
corresponding PGDDR bit is set to 1, and as input
ports when the bit is cleared to 0.
When the &6 output enable bits (CS3E to CS0E) are
set to 1, pins PG3 to PG0 function as &6 output pins
when the corresponding PGDDR bit is set to 1, and
as input ports when the bit is cleared to 0. When
CS3E to CS0E are cleared to 0, pins PG3 to PG0 are
I/O ports, and their functions can be switched with
PGDDR.
•
Mode 7 (when EXPE = 0)
Pins PG6 to PG0 are I/O ports, and their functions
can be switched with PGDDR.
Rev. 1.0, 09/01, page 483 of 904