Contention Between Tcor Write And Compare Match - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

ø
Address
Internal write signal
TCNT input clock
TCNT
Figure 13.11 Contention between TCNT Write and Increment
13.8.3

Contention between TCOR Write and Compare Match

During the T state of a TCOR write cycle, the TCOR write has priority and the compare match
2
signal is inhibited even if a compare match event occurs as shown in figure 13.12.
TCNT write cycle by CPU
T T
1
TCNT address
N
2
M
Counter write data
Rev. 1.0, 09/01, page 607 of 904