Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 586

16 bit single-chip microcomputer

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Example of Cascaded Operation Setting Procedure: Figure 11.17 shows an example of the

setting procedure for cascaded operation.

Cascaded operation

Examples of Cascaded Operation: Figure 11.18 illustrates the operation when counting upon

TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been

designated as input capture registers, and the TIOC pin rising edge has been selected.

When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of

the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.

Figure 11.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been

set for TCNT_1, and phase counting mode has been designated for channel 2.

TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.

Rev. 1.0, 09/01, page 542 of 904

Set cascading

Figure 11.17 Cascaded Operation Setting Procedure

Figure 11.18 Example of Cascaded Operation (1)

Set bits TPSC2 to TPSC0 in the channel 1

(channel 4) TCR to B'1111 to select TCNT_2

(TCNT_5) overflow/underflow counting.

Set the CST bit in TSTR for the upper and lower

channel to 1 to start the count operation.

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