Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 343

release
ø
Address
bus
DMA
Idle
control
Channel
Request
Minimum
of 2 cycles
[1]
[1] Acceptance after transfer enabling; the
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the write cycle is completed.
(As in [1], the
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.24 Example of '5(4
'5(4 pin sampling is performed every cycle, with the rising edge of the next ø cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the '5(4 pin low level is sampled while acceptance by means of the '5(4 pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the write cycle, acceptance resumes, '5(4 pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
Figure 7.25 shows an example of block transfer mode transfer activated by '5(4 pin low level.
Bus DMA
read
Transfer source Transfer destination
Read Write
Request clear period
[2] [3]
pin low level is sampled on the rising edge of ø, and the request is held.)
'5(4 Pin Low Level Activated Normal Mode Transfer '5(4 '5(4
DMA Bus
write release
Idle Read
Request clear period
Request
Minimum
of 2 cycles
[4] [5] [6]
Acceptance resumes
pin low level is sampled on the rising edge of ø,
DMA DMA
read write
Transfer source Transfer destination
Write Idle
[7]
Acceptance resumes
Rev. 1.0, 09/01, page 299 of 904
Bus
release