Extension Of Chip Select ( Cs ) Assertion Period - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

ø
Address bus
RDNn = 0
Data bus
RDNn = 1
Data bus
6.5.6 Extension of Chip Select (&6
Some external I/O devices require a setup time and hold time between address and &6 signals and
strobe signals such as 5', +:5, and /:5. Settings can be made in the CSACR register to insert
states in which only the &6, $6, and address signals are asserted before and after a basic bus space
access cycle. Extension of the &6 assertion period can be set for individual areas. With the &6
assertion extension period in write access, the data setup and hold times are less stringent since the
write data is output to the data bus.
Figure 6.20 shows an example of the timing when the &6 assertion period is extended in basic bus
3-state access space.
Rev. 1.0, 09/01, page 154 of 904
T
,
Figure 6.19 Example of Read Strobe Timing
&6) Assertion Period
&6 &6
Bus cycle
T
1 2
T
3