Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 169

Bit Bit Name
5 DDS
4 EDDS
−
3
Initial Value R/W
0 R/W
0 R/W
0 R/W
Description
DMAC Single Address Transfer Option
Selects whether full access is always performed
or burst access is enabled when DMAC single
address transfer is performed on the
DRAM/synchronous DRAM .
When the BE bit is cleared to 0 in DRAMCR,
disabling DRAM/synchronous DRAM burst
access, DMAC single address transfer is
performed in full access mode regardless of the
setting of this bit.
This bit has no effect on other bus master
external accesses or DMAC dual address
transfers.
0: Full access is always executed
1: Burst access is enabled
EXDMAC Single Address Transfer Option
Selects whether full access is always performed
or burst access is enabled when EXDMAC
single address transfer is performed on the
DRAM/synchronous DRAM.
When the BE bit is cleared to 0 in DRAMCR,
disabling DRAM/synchronous DRAM burst
access, EXDMAC single address transfer is
performed in full access mode regardless of the
setting of this bit.
This bit has no effect on other bus master
external accesses or EXDMAC dual address
transfers.
0: Full access is always executed
1: Burst access is enabled
Reserved
This bit is always read as 0. The initial value
should not be changed.
Rev. 1.0, 09/01, page 125 of 904