Irq Enable Register (Ier) - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

Bit Bit Name
−
3
2 IPR2
1 IPR1
0 IPR0
5.3.3

IRQ Enable Register (IER)

IER controls enabling and disabling of interrupt requests IRQ15 to IRQ0.
Bit Bit Name
15 IRQ15E
14 IRQ14E
13 IRQ13E
12 IRQ12E
11 IRQ11E
10 IRQ10E
Rev. 1.0, 09/01, page 78 of 904
Initial Value R/W
−
0
1 R/W
1 R/W
1 R/W
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Reserved
This bit is always read as 0 and cannot be
modified.
Sets the priority of the corresponding interrupt
source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
Description
IRQ15 Enable
The IRQ15 interrupt request is enabled when
this bit is 1.
IRQ14 Enable
The IRQ14 interrupt request is enabled when
this bit is 1.
IRQ13 Enable
The IRQ13 interrupt request is enabled when
this bit is 1.
IRQ12 Enable
The IRQ12 interrupt request is enabled when
this bit is 1.
IRQ11 Enable
The IRQ11 interrupt request is enabled when
this bit is 1.
IRQ10 Enable
The IRQ10 interrupt request is enabled when
this bit is 1.