Exdmac Bus Cycles (Single Address Mode) - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

Bus release
ø
Address bus
DMA control
Idle
Channel
Request
Minimum 3 cycles
[1]
[1] Acceptance after transfer enabling;
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] DMA cycle is started.
[4], [7] Acceptance is resumed after completion of dead cycle.
(As in [1],
Figure 8.21 Example of Block Transfer Mode Transfer Activated by ('5(4
('5(4 pin sampling is performed in each cycle starting at the next rise of ø after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the ('5(4 pin while acceptance via the ('5(4 pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared. At the end of the write cycle, acceptance resumes and ('5(4 pin low level
sampling is performed again; this sequence of operations is repeated until the end of the transfer.
8.4.10

EXDMAC Bus Cycles (Single Address Mode)

Single Address Mode (Read): Figure 8.22 shows an example of transfer when (7(1' output is
enabled, and byte-size, single address mode transfer (read) is performed from external 8-bit, 2-
state access space to an external device.
Rev. 1.0, 09/01, page 354 of 904
One block transfer
DMA read DMA write
Transfer source
destination
Read Write
Request clearance period
[2] [3]
pin low level is sampled at rise of ø, and request is held.)
Bus release
Transfer
Idle Read
Request
Minimum 3 cycles
[4] [5]
Acceptance
resumed
pin low level is sampled at rise of ø, and request is held.
One block transfer
DMA read DMA write
Transfer
Transfer source
destination
Write Idle
Request clearance period
[6] [7]
Acceptance
resumed
('5(4 Pin Low Level ('5(4 ('5(4
Bus release