Multi-Channel Operation - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

16 bit single-chip microcomputer

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Internal address

Internal read signal

External address

Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function

When the write data buffer function is activated, the DMAC recognizes that the bus cycle

concerned has ended, and starts the next operation. Therefore, '5(4 pin sampling is started one

state after the start of the DMA write cycle or single address transfer.

Multi-Channel Operation

The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table

7.11 summarizes the priority order for DMAC channels.

Table 7.11 DMAC Channel Priority Order

Short Address Mode

If transfer requests are issued simultaneously for more than one channel, or if a transfer request for

another channel is issued during a transfer, when the bus is released, the DMAC selects the

highest-priority channel from among those issuing a request according to the priority order shown

in table 7.11. During burst transfer, or when one block is being transferred in block transfer, the

channel will not be changed until the end of the transfer. Figure 7.34 shows a transfer example in

which transfer requests are issued simultaneously for channels 0A, 0B, and 1.

Full Address Mode

Rev. 1.0, 09/01, page 307 of 904

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