Figure 22.2 Software Standby Mode Application Example........................................................811
Figure 22.3 Hardware Standby Mode Timing ............................................................................812
Section 24 Electrical Characteristics
Figure 24.1 Output Load Circuit.................................................................................................855
Figure 24.2 System Clock Timing ..............................................................................................856
Figure 24.3 SDRAM φ Timing* ..................................................................................................857
Figure 24.4 (1) Oscillation Stabilization Timing ........................................................................857
Figure 24.4 (2) Oscillation Stabilization Timing ........................................................................858
Figure 24.5 Reset Input Timing ..................................................................................................859
Figure 24.6 Interrupt Input Timing .............................................................................................859
Figure 24.7 Basic Bus Timing: Two-State Access .....................................................................863
Figure 24.8 Basic Bus Timing: Three-State Access ...................................................................864
Figure 24.9 Basic Bus Timing: Three-State Access, One Wait ..................................................865
Figure 24.10 Basic Bus Timing: Two-State Access (CS Assertion Period Extended) ...............866
Figure 24.11 Basic Bus Timing: Three-State Access (CS Assertion Period Extended) .............867
Figure 24.12 Burst ROM Access Timing: One-State Burst Access............................................868
Figure 24.13 Burst ROM Access Timing: Two-State Burst Access ...........................................869
Figure 24.14 DRAM Access Timing: Two-State Access ...........................................................870
Figure 24.15 DRAM Access Timing: Two-State Access, One Wait ..........................................871
Figure 24.16 DRAM Access Timing: Two-State Burst Access..................................................872
Figure 24.17 DRAM Access Timing: Three-State Access (RAST = 1) .....................................873
Figure 24.18 DRAM Access Timing: Three-State Burst Access................................................874
Figure 24.19 CAS-Before-RAS Refresh Timing ........................................................................875
Figure 24.20 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion) ...........................875
Figure 24.21 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) .............875
Figure 24.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) .............876
Figure 24.23 External Bus Release Timing ................................................................................876
Figure 24.24 External Bus Request Output Timing....................................................................877
Figure 24.25 Synchronous DRAM Basic Access Timing (CAS Latency 2)...............................878
Figure 24.26 Synchronous DRAM Self-Refresh Timing............................................................879
Figure 24.27 Read Data: Two-State Expansion (CAS Latency 2)..............................................880
Figure 24.28 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access .......882
Figure 24.29 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access .....883
Figure 24.30 DMAC and EXDMAC TEND/ETEND Output Timing........................................884
Figure 24.31 DMAC and EXDMAC DREQ/EDREQ Input Timing ..........................................884
Figure 24.32 EXDMAC EDRAK Output Timing ......................................................................884
Figure 24.33 I/O Port Input/Output Timing................................................................................886
Figure 24.34 PPG Output Timing ...............................................................................................886
Figure 24.35 TPU Input/Output Timing .....................................................................................887
Figure 24.36 TPU Clock Input Timing .......................................................................................887
Figure 24.37 8-Bit Timer Output Timing ...................................................................................887
Figure 24.38 8-Bit Timer Clock Input Timing............................................................................887
Figure 24.39 8-Bit Timer Reset Input Timing ............................................................................888
Rev. 1.0, 09/01, page xxxvi of xliv