Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 227

Table 6.9 Synchronous DRAM Interface Pins
With
Synchronous
Pin DRAM Setting
&65 5$6
&66 &$6
&67 :(
&68
SDRAMφ
(2() (CKE)
8&$6
DQMU
/&$6
DQML
A15 to A0 A15 to A0
D15 to D0 D15 to D0
DCTL DCTL
Name
Row address strobe
Column address strobe
Write enable
Clock
Clock enable
Upper data mask enable Output
Lower data mask enable Output
Address pins
Data pins
Device control pin
I/O Function
Output Row address strobe when
areas 2 to 5 are designated
as continuous synchronous
DRAM space
Output Column address strobe when
areas 2 to 5 are designated
as continuous synchronous
DRAM space
Output Write enable strobe when
areas 2 to 5 are designated
as continuous synchronous
DRAM space
Output Clock only for synchronous
DRAM
Output Clock enable signal when
areas 2 to 5 are designated
as continuous synchronous
DRAM space
Upper data mask enable for
16-bit continuous
synchronous DRAM space
access/data mask enable for
8-bit continuous synchronous
DRAM space access
Lower data mask enable
signal for 16-bit continuous
synchronous DRAM space
access
Output Row address/column address
multiplexed output pins
I/O Data input/output pins
Input Output enable pin for
SDRAMφ
Rev. 1.0, 09/01, page 183 of 904