Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 536

5$68/SDRAMφ φ φ φ *
&68/5$68
&68 &68 5$68 5$68
PH1/&68
The pin function is switched as shown below according to the operating mode, DCTL pin, bit
EXPE, bit CS5E, bits RMTS2 to RMTS0, and bit PH1DDR.
1
DCTL*
Operating
mode
EXPE
Area 5 Normal space
DCTL
CS5E 0
PH1DDR 0 1
Pin function PH1 PH1
input output
Notes: 1. When SDRAM interface is not used, input a low-level signal on the DCTL pin.
2. Not used in H8S/2378 series.
&67/5$67 5$67/:( :(*
&67 &67 5$67 5$67 :( :(
PH0/&67
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
CS4E, bits RMTS2 to RMTS0, and bit PH0DDR.
Operating
mode
EXPE
Area 4 —
CS4E 0
PH0DDR 0 1
Pin function PH0 PH0
input output
Note: Not used in H8S/2378 series.
Rev. 1.0, 09/01, page 492 of 904
2
1, 2, 4, 5, 6
—
DRAM space
1 0
0 1 0 1
&68 5$68
PH1 PH1 PH1
input output input output output
1, 2, 4, 5, 6
—
Normal space DRAM
space
1
0 1 —
&67 5$67
PH0
input output output
0
0
— Normal space
0
1 — 0
— 0 1 0
PH1 PH1 PH1
input output input output
0
Syn- —
chronous
DRAM*
space
—
— 0 1
:(*
PH0 PH0
output input output
7
1
DRAM space
1 0
1 0 1 0
&68
PH1 PH1 PH1 PH1
input output input output
7
1
— Normal space
0
0 1 0 1
&67
PH0 PH0 PH0
input output input output
1
—
—
—
1
1 —
1 — —
5$68
2
SDRAM*
φ output
output
DRAM Syn-
space chronous
DRAM*
space
1
— —
5$67 :(*
output output