Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 254

(2) Read Data Extension
If the CKSPE bit is set to 1 in DRACCR when the continuous synchronous DRAM space is read-
accessed in DMAC/EXDMAC single address mode, the establishment time for the read data can
be extended by clock suspend mode. The number of states for insertion of the read data extension
cycle (Tsp) is set in bits RDXC1 and RDXC0 in DRACCR. Be sure to set the OEE bit to 1 in
DRAMCR when the read data will be extended. The extension of the read data is not in
accordance with the bits DDS and EDDS.
Figure 6.62 shows the timing chart when the read data is extended by two cycles.
Address bus
Precharge-sel
DQMU, DQML
Figure 6.62 Example of Timing when the Read Data is Extended by Two States
(DDS = 1, or EDDS = 1, RDXC1 = 0, RDXC0 = 1, CAS Latency 2)
Rev. 1.0, 09/01, page 210 of 904
T
p
ø
SDRAMø
Column
address
CKE
Data bus
or
PALL ACTV
T T T T
r c1 cl c2
Row
address
Row
address
READ NOP
T T
sp1 sp2
Column address