Operation; Watchdog Timer Mode - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

14.4

Operation

14.4.1

Watchdog Timer Mode

To use the WDT as a watchdog timer mode, set the WT/,7 and TME bits in TCSR to 1.
If TCNT overflows without being rewritten because of a system crash or other error, the
:'729) signal is output.
This ensures that TCNT does not overflow while the system is operating normally. Software must
prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before
overflow occurs. This :'729) signal can be used to reset the chip internally in watchdog timer
mode.
If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets this LSI
internally is generated at the same time as the :'729) signal. If a reset caused by a signal input
to the 5(6 pin occurs at the same time as a reset caused by a WDT overflow, the 5(6 pin reset
has priority and the WOVF bit in RSTCSR is cleared to 0.
The :'729) signal is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0.
The internal reset signal is output for 518 states.
When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If TCNT
overflows when 1 is set in the RSTE bit in RSTCSR, an internal reset signal is generated to the
entire chip.
Rev. 1.0, 09/01, page 618 of 904