Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 621

Bit Bit Name
7 —
to
4
3 NDR11
2 NDR10
1 NDR9
0 NDR8
NDRL
If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same
address and can be accessed at one time, as shown below.
Bit Bit Name
7 NDR7
6 NDR6
5 NDR5
4 NDR4
3 NDR3
2 NDR2
1 NDR1
0 NDR0
If pulse output groups 0 and 1 have different output triggers, upper 4 bits and lower 4 bits are
mapped to the different addresses as shown below.
Bit Bit Name
7 NDR7
6 NDR6
5 NDR5
4 NDR4
3 —
to
0
Initial Value R/W
1 —
0 R/W
0 R/W
0 R/W
0 R/W
Initial Value R/W
0
R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 —
Description
Reserved
1 is always read and write is disabled.
Next Data Register 11 to 8
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
Description
Next Data Register 7 to 0
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Description
Next Data Register 7 to 4
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Reserved
1 is always read and write is disabled.
Rev. 1.0, 09/01, page 577 of 904