Activation Source Acceptance; Internal Interrupt After End Of Transfer; Channel Re-Setting - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer
is enabled is performed on detection of a low level.
7.7.6

Activation Source Acceptance

At the start of activation source acceptance, a low level is detected in both '5(4 pin falling edge
sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request
is detected. Therefore, a request is accepted from an internal interrupt or '5(4 pin low level that
occurs before write to DMABCRL to enable transfer.
When the DMAC is activated, take any necessary steps to prevent an internal interrupt or '5(4
pin low level remaining from the end of the previous transfer, etc.
7.7.7

Internal Interrupt after End of Transfer

When the DTE bit in DMABCRL is cleared to 0 at the end of a transfer or by a forcible
termination, the selected internal interrupt request will be sent to the CPU or DTC even if the
DTA bit in DMABCRH is set to 1.
Also, if internal DMAC activation has already been initiated when operation is forcibly
terminated, the transfer is executed but flag clearing is not performed for the selected internal
interrupt even if the DTA bit is set to 1.
An internal interrupt request following the end of transfer or a forcible termination should be
handled by the CPU as necessary.
7.7.8

Channel Re-Setting

To reactivate a number of channels when multiple channels are enabled, use exclusive handling of
transfer end interrupts, and perform DMABCR control bit operations exclusively.
Note, in particular, that in cases where multiple interrupts are generated between reading and
writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the
DMABCR write data in the original interrupt handling routine will be incorrect, and the write may
invalidate the results of the operations by the multiple interrupts. Ensure that overlapping
DMABCR operations are not performed by multiple interrupts, and that there is no separation
between read and write operations by the use of a bit-manipulation instruction.
Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must
first be read while cleared to 0 before the CPU can write 1 to them.
Rev. 1.0, 09/01, page 316 of 904