Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 66

16 bit single-chip microcomputer

Table of Contents

• Exception vector table and memory indirect branch addresses

In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table

in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the

lower 24 bits (see figure 2.3). For details of the exception vector table, see section 4, Exception

Figure 2.3 Exception Vector Table (Advanced Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions

uses an 8-bit absolute address included in the instruction code to specify a memory operand

that contains a branch address. In advanced mode, the operand is a 32-bit longword operand,

providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is

regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.

Note that the top area of this range is also used for the exception vector table.

• Stack structure

In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine

call, and the PC, condition-code register (CCR), and extended control register (EXR) are

pushed onto the stack in exception handling, they are stored as shown in figure 2.4. EXR is not

pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception

Rev. 1.0, 09/01, page 22 of 904

Reset exception vector

(Reserved for system use)

Exception vector 1

Exception vector table

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