C Bus Status Register (Icsr) - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

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16.3.5 I

C Bus Status Register (ICSR)

ICSR is an 8-bit readable/writable register that performs confirmation of interrupt request flags
and status.
Bit Bit Name Initial Value R/W
7 TDRE 0
6 TEND 0
5 RDRF 0
4 NACKF 0
3 STOP 0
2 AL 0
Description
R/W Transmit Data Register Empty
[Setting condition]
•
When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
[Clearing conditions]
•
When 0 is written in TDRE after reading TDRE = 1
R/W Transmit end
[Setting conditions]
•
When the ninth clock of SCL is rose while the TDRE flag
is 1
[Clearing conditions]
•
When 0 is written in TEND after reading TEND = 1
R/W Receive Data Register Full
[Setting condition]
•
When a received data is transferred from ICDRS to
ICDRR
[Clearing conditions]
•
When 0 is written in RDRF after reading RDRF = 1
R/W No acknowledge detection flag
[Setting condition]
•
When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER is 1
[Clearing condition]
•
When 0 is written in NACKF after reading NACKF = 1
R/W Stop condition detection flag
[Setting condition]
•
When a stop condition is detected after frame transfer
[Clearing condition]
•
When 0 is written in STOP after reading STOP = 1
R/W Arbitration Lost Flag
This flag indicates that arbitration was lost in master mode.
When two or more master devices attempt to seize the bus
at nearly the same time, if the I
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C bus interface detects data
Rev. 1.0, 09/01, page 717 of 904