Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 27

Figure 6.41 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1
(RAST = 0, CAST = 0) ...........................................................................................178
Figure 6.42 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0
(RAST = 0, CAST = 1) ............................................................................................179
Figure 6.43 Relationship between φ and SDRAM φ
(when PLL frequency multiplication factor is × 1 or × 2) .........................................184
Figure 6.44 Basic Access Timing of Synchronous DRAM (CAS Latency 1) ............................185
Figure 6.45 CAS Latency Control Timing (SDWCD = 0, CAS Latency 3) ...............................187
Figure 6.46 Example of Access Timing when Row Address Output Hold State is 1 State
(RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2) ...........................................189
Figure 6.47 Example of Timing with Two-State Precharge Cycle
(TPC1 = 0, TPC0 = 1, SDWCD = 0, CAS Latency 2)............................................191
Figure 6.48 Example of Write Access Timing when CAS Latency Control Cycle is Disabled
(SDWCD = 1) ..........................................................................................................192
Figure 6.49 DQMU and DQML Control Timing (Upper Byte Write Access: SDWCD = 0,
CAS Latency 2)........................................................................................................193
Figure 6.50 DQMU and DQML Control Timing (Lower Byte Read Access: CAS Latency 2) .194
Figure 6.51 Example of DQMU and DQML Byte Control.........................................................195
Figure 6.52 Operation Timing of Burst Access (BE = 1, SDWCD = 0, CAS Latency 2) .........197
Figure 6.53 Example of Operation Timing in RAS Down Mode (BE = 1, CAS Latency 2) .....198
Figure 6.54 Auto Refresh Timing ...............................................................................................200
Figure 6.55 Auto Refresh Timing (TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1) .....................201
Figure 6.56 Auto Refresh Timing (TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1) .....................202
Figure 6.57 Self-Refresh Timing (TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0,
RLW0 = 0) ...............................................................................................................203
Figure 6.58 Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2) ........204
Figure 6.59 Synchronous DRAM Mode Setting Timing ............................................................205
Figure 6.60 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1 ............207
Figure 6.61 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0 ............209
Figure 6.62 Example of Timing when the Read Data is Extended by Two States
(DDS = 1, or EDDS = 1, RDXC1 = 0, RDXC0 = 1, CAS Latency 2) ..................210
Figure 6.63 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle)..............212
Figure 6.64 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle)..............213
Figure 6.65 Example of Idle Cycle Operation (Consecutive Reads in Different Areas)..............214
Figure 6.66 Example of Idle Cycle Operation (Write after Read) ..............................................215
Figure 6.67 Example of Idle Cycle Operation (Read after Write) ..............................................216
Figure 6.68 Relationship between Chip Select (CS) and Read (RD)..........................................217
Figure 6.69 Example of DRAM Full Access after External Read (CAST = 0) ..........................217
Figure 6.70 Example of Idle Cycle Operation in RAS Down Mode
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)..........218
Figure 6.71 Example of Idle Cycle Operation in RAS Down Mode (Write after Read)
(IDLC = 0, RAST = 0, CAST = 0)..........................................................................218
Rev. 1.0, 09/01, page xxvii of xliv