Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 408

ø pin
CPU cycle CPU cycle CPU cycle
Bus cycle
External External
CPU
space space
operation
Figure 8.36 External Request/Cycle Steal Mode/Normal Transfer Mode
(CPU Cycles/Single Address Mode/Low Level Sensing)
ø pin
Edge confirmation
acceptance
Start of transfer
internal
processing
processing
state
Bus cycle Bus release
Figure 8.37 External Request/Cycle Steal Mode/Normal Transfer Mode
(No Contention/Single Address Mode/Falling Edge Sensing)
Rev. 1.0, 09/01, page 364 of 904
EXDMA single
transfer cycle
External External
space space
Start of high
Edge confirmation
level sensing Start of transfer
processing
EXDMA single
Bus release
transfer cycle
2 bus cycles Last transfer cycle
CPU cycle CPU cycle
External External
space
Start of high
Edge confirmation
level sensing Start of transfer
processing
EXDMA single
Bus release
transfer cycle
EXDMA single
CPU cycle
transfer cycle
space
Start of high
level sensing
EXDMA single
transfer cycle