Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 183

ROM interface that allows direct connection of burst ROM. The interface can be selected
independently for each area.
An area for which the basic bus interface is designated functions as normal space, an area for
which the DRAM interface is designated functions as DRAM space, an area for which the
synchronous DRAM interface is designated functions as continuous synchronous DRAM space,
and an area for which the burst ROM interface is designated functions as burst ROM space.
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode.
Note: * The synchronous DRAM interface is not supported in the H8S/2378 series.
Area 0: Area 0 includes on-chip ROM in expanded mode with on-chip ROM enabled and the
space excluding on-chip ROM is external address space, and in expanded mode with on-chip
ROM disabled, all of area 0 is external address space.
When area 0 external space is accessed, the &63 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 0.
Area 1: In externally expanded mode, all of area 1 is external address space.
When area 1 external address space is accessed, the &64 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 1.
Areas 2 to 5: In externally expanded mode, areas 2 to 5 are all external address space.
When area 2 to 5 external space is accessed, signals &65 to &68 can be output.
Basic bus interface, DRAM interface, or synchronous DRAM interface can be selected for areas 2
to 5. With the DRAM interface, signals &65 to &68 are used as 5$6 signals.
If areas 2 to 5 are designated as continuous DRAM space, large-capacity (e.g. 64-Mbit) DRAM
can be connected. In this case, the &65 signal is used as the 5$6 signal for the continuous DRAM
space.
If areas 2 to 5 are designated as continuous synchronous DRAM space, large-capacity (e.g. 64-
Mbit) synchronous DRAM can be connected. In this case, the &65, &66, &67, and &68 pins are
used as the 5$6, &$6, :(, and CLK signals for the continuous synchronous DRAM space. The
2( pin is used as the CKE signal.
Area 6: In externally expanded mode, all of area 6 is external space.
When area 6 external space is accessed, the &69 signal can be output.
Rev. 1.0, 09/01, page 139 of 904