Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 685

Bit Bit Name
3 PER
2 TEND
1 MPB
0 MPBT
Note: * Only 0 can be written, to clear the flag.
Initial Value R/W
0 R/(W)*
1 R
0 R
0 R/W
Description
Parity Error
Indicates that a parity error occurred while
receiving in asynchr onous m ode and the reception
has ended abnormally.
[Setting condition]
•
When a parity error is detected during
reception
I f a par i t y er r or occur s, t he r ecei ve dat a i s
t r ansf er r ed t o R D R but t he R D R F f l ag i s not set .
Al so, subsequent ser i al r ecept i on cannot be
cont i nued w hi l e t he PER f l ag i s set t o 1. I n
cl ocked synchr onous m ode, ser i al t r ansm i ssi on
cannot be cont i nued, ei t her .
[Clearing condition]
•
When 0 is written to PER after reading PER =
1
The PER flag is not affected and retains its
previous state when the RE bit in SCR is cleared
to 0.
Transmit End
[Setting conditions]
•
When the TE bit in SCR is 0
•
When TDRE = 1 at transmission of the last bit
of a 1-byte serial transmit character
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE
= 1
•
When the DMAC or DTC is activated by a TXI
interrupt and writes data to TDR
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive
data. When the RE bit in SCR is cleared to 0 its
previous state is retained.
Multiprocessor Bit Transfer
MPBT sets the multiprocessor bit to be added to
the transmit data.
Rev. 1.0, 09/01, page 641 of 904