Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 270

ø
Address bus
Precharge-sel
CKE
DQMU, DQML
,
Data bus
Figure 6.80 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2)
Table 6.11 shows whether there is an idle cycle insertion or not in the case of mixed accesses to
normal space and DRAM space/continuous synchronous DRAM space.
Rev. 1.0, 09/01, page 226 of 904
Continuous synchronous
DRAM space write
T T T T
p r c1 c2
Row
Column Column
address
address
address
Row
address
PALL ACTV NOP WRIT
External address space read
T T T
i 1 2
External address
External address
High
NOP
Idle cycle
Synchronous
DRAM space read
T T T T
3 c1 Cl c2
Column address 2
READ NOP