Address Multiplexing - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

6.7.2

Address Multiplexing

With continuous synchronous DRAM space, the row address and column address are multiplexed.
In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to
MXC0 in DRAMCR. The address-precharge-setting command (Prechrge-sel) can be output on the
upper column address. Table 6.8 shows the relation between the settings of MXC2 to MXC0 and
the shift size. The MXC2 bit should be set to 1 when the synchronous DRAM interface is used.
Table 6.8 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing
DRAMCR
MXC2 MXC1 MXC0
Row 0 x x
address
1 0 0
1
1 0
1
Column 0 x x
address
1 0 0
1
1 0
1
X: Don't care.
P: Precharge-sel
A23 to
Shift A16
Size A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
8 bits A23 to A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8
A16
9 bits A23 to A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
A16
10 bits A23 to A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
A16
11 bits A23 to A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
A16
— A23 to P P P
A16
— A23 to P P P
A16
— A23 to P P P
A16
— A23 to P P P
A16
Address Pins
Reserved (setting prohibited)
Reserved (setting prohibited)
P P P P A8 A7 A6 A5 A4 A3 A2 A1 A0
P P P A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
P P A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
P A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Rev. 1.0, 09/01, page 181 of 904