Wait Control; Write Access - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

Upper address bus
Lower address bus
6.8.2

Wait Control

As with the basic bus interface, either program wait insertion or pin wait insertion using the :$,7
pin can be used in the initial cycle (full access) on the burst ROM interface. See section 6.5.5,
Wait Control. Wait states cannot be inserted in a burst cycle.
6.8.3

Write Access

When a write access to burst ROM space is executed, burst access is interrupted at that point and
the write access is executed in line with the basic bus interface settings. Write accesses are not
performed in burst mode even though burst ROM space is designated.
T
ø
Data bus
Note: n = 1 and 0
Figure 6.64 Example of Burst ROM Access Timing
(ASTn = 0, 1-State Burst Cycle)
Full access Burst access
T T
1 2 1
T
1
Rev. 1.0, 09/01, page 213 of 904