Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 245

T T T T T T
Rp1 Rp2 Rrw Rr Rc1 Rc2
ø
SDRAMø
Address bus
Precharge-sel
CKE
High
PALL NOP REF NOP
Figure 6.55 Auto Refresh Timing
(TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1)
When the interval specification from the REF command to the ACTV cannot be satisfied, setting
the RLW1 and RLW0 bits of REFCR enables one to three wait states to be inserted in the refresh
cycle. Set the optimum number of waits according to the synchronous DRAM connected and the
operating frequency of this LSI. Figure 6.56 shows the timing when one wait state is inserted.
Rev. 1.0, 09/01, page 201 of 904