Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 295

Full Address Mode:
• DMACR_0A and DMACR_1A
Bit Bit Name
15 DTSZ
14 SAID
13 SAIDE
12 BLKDIR
11 BLKE
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Data Transfer Size
Selects the size of data to be transferred at one
time.
0: Byte-size transfer
1: Word-size transfer
Source Address Increment/Decrement
Source Address Increment/Decrement Enable
These bits specify whether source address
register MARA is to be incremented,
decremented, or left unchanged, when data
transfer is performed.
00: MARA is fixed
01: MARA is incremented after a data transfer
•
When DTSZ = 0, MARA is incremented by 1
•
When DTSZ = 1, MARA is incremented by 2
10: MARA is fixed
11: MARA is decremented after a data transfer
•
When DTSZ = 0, MARA is decremented by
1
•
When DTSZ = 1, MARA is decremented by
2
Block Direction
Block Enable
These bits specify whether normal mode or
block transfer mode is to be used for data
transfer. If block transfer mode is specified, the
BLKDIR bit specifies whether the source side or
the destination side is to be the block area.
x0: Transfer in normal mode
01: Transfer in block transfer mode (destination
side is block area)
11: Transfer in block transfer mode (source side
is block area)
Rev. 1.0, 09/01, page 251 of 904