Serial Control Register (Scr) - Hitachi H8/3062 Hardware Manual

For the relationship between the clock source, bit rate register setting, and baud rate, see section
12.2.8, Bit Rate Register (BRR).
Bit 1 Bit 0
CKS1 CKS0
0 0
0 1
1 0
1 1
12.2.6

Serial Control Register (SCR)

SCR register enables or disables the SCI transmitter and receiver, enables or disables serial clock
output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock
source.
Bit 7
TIE
Initial value 0
Read/Write
R/W
Description
φ
φ/4
φ/16
φ/64
6 5
RIE TE
0 0
R/W R/W
Transmit enable
Enables or disables the transmitter
Receive interrupt enable
Enables or disables receive-data-full interrupts (RxI) and
receive-error interrupts (ERI)
Transmit interrupt enable
Enables or disables transmit-data-empty interrupts (TxI)
4
3 2
RE MPIE TEIE
0 0 0
R/W R/W
R/W
Multiprocessor interrupt enable
Enables or disables multiprocessor
interrupts
Receive enable
Enables or disables the receiver
(Initial value)
1 0
CKE1 CKE0
0 0
R/W
R/W
Clock enable 1/0
These bits select the
SCI clock source
Transmit-end interrupt enable
Enables or disables transmit-end
interrupts (TEI)
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