Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 347

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Address bus
Bus
release
Figure 7.29 Example of Single Address Mode Transfer (Word Write)
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
'5(4 Pin Falling Edge Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel '5(4
'5(4 '5(4
for which the '5(4 pin is selected.
Figure 7.30 shows an example of single address mode transfer activated by the '5(4 pin falling
edge.
DMA write
Bus
release
DMA write
Bus
release
Rev. 1.0, 09/01, page 303 of 904
DMA
DMA write dead
Last transfer Bus
cycle release