15.10.6 Restrictions On Use Of Dmac Or Dtc; 15.10.7 Operation In Case Of Mode Transition - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is
written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has
not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1
before writing transmit data to TDR.

15.10.6 Restrictions on Use of DMAC or DTC

• When an external clock source is used as the serial clock, the transmit clock should not be
input until at least 5 ø clock cycles after TDR is updated by the DMAC or DTC. Misoperation
may occur if the transmit clock is input within 4 ø clocks after TDR is updated. (Figure 15.35)
• When RDR is read by the DMAC or DTC, be sure to set the activation source to the relevant
SCI receive-data-full interrupt (RXI).
SCK
TDRE
Serial data
Note: When operating on an external clock, set t > 4 clocks.
Figure 15.35 Example of Synchronous Transmission Using DTC

15.10.7 Operation in Case of Mode Transition

• Transmission
Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module
stop mode or software standby mode transition. TSR, TDR, and SSR are reset. The output pin
states in module stop mode or software standby mode depend on the port settings, and become
high-level output after the relevant mode is cleared. If a transition is made during
transmission, the data being transmitted will be undefined.
When transmitting without changing the transmit mode after the relevant mode is cleared,
transmission can be started by setting TE to 1 again, and performing the following sequence:
SSR read → TDR write → TDRE clearance. To transmit with a different transmit mode after
clearing the relevant mode, the procedure must be started again from initialization.
Figure 15.36 shows a sample flowchart for mode transition during transmission. Port pin states
during mode transition are shown in figures 15.37 and 15.38.
Rev. 1.0, 09/01, page 702 of 904
t
LSB
D0 D1 D2 D3 D4 D5 D6 D7