Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 152

Name
Chip select 4/row address
strobe 4/write enable
Chip select 5/row address
strobe 5/SDRAMφ
Chip select 6
Chip select 7
Upper column address
strobe/upper data mask enable
Lower column address strobe/
lower data mask enable
Output enable/clock enable
Wait
Bus request
Bus request acknowledge
Rev. 1.0, 09/01, page 108 of 904
Symbol I/O
&67/
Output
5$67/
:(*
&68/
Output
5$68/
SDRAMφ*
&69
Output
&6:
Output
8&$6/
Output
'408*
/&$6/
Output
'40/*
2(/CKE*
Output
:$,7
Input
%5(4
Input
%$&.
Output
Function
Strobe signal indicating that area 4 is
selected, DRAM row address strobe signal
when area 4 is DRAM space, or write
enable signal of the synchronous DRAM
when the synchronous DRAM interface is
selected.
Strobe signal indicating that area 5 is
selected, DRAM row address strobe signal
when area 5 is DRAM space, or dedicated
clock signal for the synchronous DRAM
when the synchronous DRAM interface is
selected.
Strobe signal indicating that area 6 is
selected.
Strobe signal indicating that area 7 is
selected.
16-bit DRAM space upper column address
strobe signal, 8-bit DRAM space column
address strobe signal, upper data mask
signal of 16-bit synchronous DRAM space,
or data mask signal of 8-bit synchronous
DRAM space.
16-bit DRAM space lower column address
strobe signal or lower data mask signal for
the 16-bit synchronous DRAM space.
Output enable signal for the DRAM space
or clock enable signal for the synchronous
DRAM space.
Wait request signal when accessing
external address space.
Request signal for release of bus to
external bus master.
Acknowledge signal indicating that bus has
been released to external bus master.