Dma Terminal Control Register (Dmatcr) - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

7.3.7

DMA Terminal Control Register (DMATCR)

DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can
be set for output automatically, and a transfer end signal output, by setting the appropriate bit.
Bit Bit Name

7

6
5 TEE1
4 TEE0

3
to
0
Rev. 1.0, 09/01, page 268 of 904
Initial Value R/W

0

0
0 R/W
0 R/W

0
Description
Reserved
These bits are always read as 0 and cannot be
modified.
Transfer End Enable 1
Enables or disables transfer end pin 1 (7(1'4)
output.
0: 7(1'4 pin output disabled
1: 7(1'4 pin output enabled
Transfer End Enable 0
Enables or disables transfer end pin 0 (7(1'3)
output.
0: 7(1'3 pin output disabled
1: 7(1'3 pin output enabled
Reserved
These bits are always read as 0 and cannot be
modified.