Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 56

Type Symbol
Bus control
RA S/RA S
2
RA S3 to
RA S5
RA S
CA S
W E
W A I T
O E
(O E)
CKE
(CKE)
Interrupt NMI
signals
I RQ 15 to
I RQ 0
(I RQ 15)
to (I RQ 0)
DMA controller
D REQ 1
(DMAC)
D REQ 0
TEN D 1
TEN D 0
D A CK 1
D A CK 0
EXDMA
ED REQ 3,
controller
ED REQ 2
(EXDMAC)
Rev. 1.0, 09/01, page 12 of 904
Pin No. I/O
109, 110, Output Row address strobe signal for the synchronous
35, 36
109 Output Row address strobe signal for the synchronous
110 Output Column address strobe signal for the synchronous
35 Output Write enable signal for the synchronous DRAM of
84 Input
38, Output Output enable signal for DRAM interface space.
137
38, Output Clock enable signal of the synchronous DRAM
137
40 Input
86, 85, Input
106 to 104,
83 to 81,
31 to 28,
136 to 133
58 to 51,
38, 37,
61 to 59,
34, 33, 3
82, Input
81
104, Output These signals indicate the end of DMAC data
83
106, Output DMAC single address transfer acknowledge signals.
105
33, Input
3
Function
DRAM interface.
RA S signal is a row address strobe signal when
areas 2 to 5 are set to the continuous DRAM space.
DRAM of the synchronous DRAM interface.
DRAM of the synchronous DRAM interface.
the synchronous DRAM interface.
Requests insertion of a wait state in the bus cycle
when accessing external 3-state address space.
The output pins of O E and (O E) are selected by the
port function control register 2 (PFCR2) of port 3.
interface space.
The output pins of CKE and (CK E) are selected by
the port function control register 2 (PFCR2) of port
3.
Nonmaskable interrupt request pin. Fix high when
not used.
These pins request a maskable interrupt.
The input pins of I RQ n and (I RQ n) are selected by
the IRQ pin select register (ITSR) of the interrupt
controller. (n = 0 to 15)
These signals request DMAC activation.
transfer.
These signals request EXDMAC activation.