Burst Operation - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

16 bit single-chip microcomputer

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(Address shift size set to 8 bits)

Figure 6.51 Example of DQMU and DQML Byte Control

Burst Operation

With synchronous DRAM, in addition to full access (normal access) in which data is accessed by

outputting a row address for each access, burst access is also provided which can be used when

making consecutive accesses to the same row address. This access enables fast access of data by

simply changing the column address after the row address has been output. Burst access can be

selected by setting the BE bit to 1 in DRAMCR.

Notes: 1. Bank control is not available.

2. The CKE and

pin must be fixed to 0 before accessing synchronous DRAM.

16-Mbit synchronous DRAM

1 Mword × 16 bits × 4-bank configuration

8-bit column address

pins must be fixed to 1 when the power supply is input.

Rev. 1.0, 09/01, page 195 of 904

input: A11 to A0

Column address

input: A7 to A0

address: A13/A12

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