All-Module-Clocks-Stop Mode; Ø Clock Output Control - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

The module registers which are set in module stop mode cannot be read or written to.
22.2.6

All-Module-Clocks-Stop Mode

When the ACSE bit in MSTPCRH is set to 1 and module stop mode is set for all the on-chip
peripheral functions controlled by MSTPCR (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF), or for
all the on-chip peripheral functions except the 8-bit timer (MSTPCR = H'FFFE, EXMSTPCR =
H'FFFF), executing a SLEEP instruction while the SSBY bit in SBYCR is cleared to 0 will cause
all the on-chip peripheral functions (except the 8-bit timer and watchdog timer), the bus controller,
and the I/O ports to stop operating, and a transition to be made to all-module-clocks-stop mode, at
the end of the bus cycle.
Operation or halting of the 8-bit timer can be selected by means of the MSTP0 bit.
All-module-clocks-stop mode is cleared by an external interrupt (NMI, ,543#to ,5448 pins), 5(6
pin input, or an internal interrupt (8-bit timer, watchdog timer), and the CPU returns to the normal
program execution state via the exception handling state. All-module-clocks-stop mode is not
cleared if interrupts are disabled, if interrupts other than NMI are masked by the CPU, or if the
relevant interrupt is designated as a DTC activation source.
When the 67%< pin is driven low, a transition is made to hardware standby mode.
22.3 ø Clock Output Control
Output of the ø clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the ø clock stops at the end of the bus cycle,
and ø output goes high. ø clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, ø clock output is disabled and input port mode is set.
Table 22.3 shows the state of the ø pin in each processing state.
Table 22.3 ø Pin State in Each Processing State
Register Setting
DDR PSTOP
Normal
operating state
0 X High impedance
1 0 ø output
1 1 Fixed high
Software
Sleep mode standby mode
High impedance High impedance
ø output Fixed high
Fixed high Fixed high
Hardware
standby mode
High impedance
High impedance
High impedance
Rev. 1.0, 09/01, page 813 of 904
All-module-
clocks-stop
mode
High impedance
ø output
Fixed high