Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 214

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Address bus
( )
,
( )
( )
Read
Data bus
( )
Write
( )
Data bus
Note: n = 2 to 5
The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion
method and timing are the same as for full access. For details see section 6.6.9, Wait Control.
RAS Down Mode and RAS Up Mode: Even when burst operation is selected, it may happen that
access to DRAM space is not continuous, but is interrupted by access to another space. In this
case, if the 5$6 signal is held low during the access to the other space, burst operation can be
resumed when the same row address in DRAM space is accessed again.
• RAS Down Mode
To select RAS down mode, set both the RCDM bit and the BE bit to 1 in DRAMCR. If access
to DRAM space is interrupted and another space is accessed, the 5$6 signal is held low
during the access to the other space, and burst access is performed when the row address of the
next DRAM space access is the same as the row address of the previous DRAM space access.
Figure 6.32 shows an example of the timing in RAS down mode.
Note, however, that the 5$6 signal will go high if:
 a refresh operation is initiated in the RAS down state
 self-refreshing is performed
 the chip enters software standby mode
 the external bus is released
Rev. 1.0, 09/01, page 170 of 904
T T
p r
Row address
High
High
Figure 6.31 Operation Timing in Fast Page Mode
(RAST = 0, CAST = 1)
T T T
c1 c2 c3
Column address 1
T T T
c1 c2 c3
Column address 2