Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 262

In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid
and an idle cycle is inserted. The timing in this case is illustrated in figures 6.70 and 6.71.
ø
Address bus
,
Data bus
Figure 6.70 Example of Idle Cycle Operation in RAS Down Mode
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)
ø
Address bus
,
Data bus
Figure 6.71 Example of Idle Cycle Operation in RAS Down Mode
Rev. 1.0, 09/01, page 218 of 904
DRAM space read
T T T
p r c1
DRAM space read
T T T
p r c1
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)
External read
T T T T
c2 1 2 3
External read
T T T T
c2 1 2 3
DRAM space read
T T T
i c1 c2
Idle cycle
DRAM space write
T T T
i c1 c2
Idle cycle