Register
Reset
Name
PORTG
Initialized
P1DR
Initialized
P2DR
Initialized
P3DR
Initialized
P5DR
Initialized
P6DR
Initialized
P8DR
Initialized
PADR
Initialized
PBDR
Initialized
PCDR
Initialized
PDDR
Initialized
PEDR
Initialized
PFDR
Initialized
PGDR
Initialized
PORTH
Initialized
PHDR
Initialized
PHDDR
Initialized
SMR_0
Initialized
BRR_0
Initialized
SCR_0
Initialized
TDR_0
Initialized
SSR_0
Initialized
RDR_0
Initialized
SCMR_0
Initialized
SMR_1
Initialized
BRR_1
Initialized
SCR_1
Initialized
TDR_1
Initialized
SSR_1
Initialized
RDR_1
Initialized
SCMR_1
Initialized
SMR_2
Initialized
BRR_2
Initialized
Clock
High-
Division Sleep
Speed
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Module
All Module
Software
Stop
Clock Stop
Standby
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Initialized Initialized
Initialized Initialized
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Initialized Initialized
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Initialized Initialized
Initialized Initialized
Initialized Initialized
Initialized Initialized
Initialized Initialized
Initialized Initialized
Initialized Initialized
Initialized Initialized
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Initialized Initialized
Rev. 1.0, 09/01, page 847 of 904
Hardware
Standby
Module
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PORT
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SCI_0
SCI_1
SCI_2