Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 26

Figure 6.4 RAS Signal Assertion Timing
(2-State Column Address Output Cycle, Full Access)...............................................128
Figure 6.5 CAS Latency Control Cycle Disable Timing during
Continuous Synchronous DRAM Space Write Access (for CAS Latency 2) ............131
Figure 6.6 Area Divisions ...........................................................................................................136
Figure 6.7 CSn Signal Output Timing (n = 0 to 7) .....................................................................141
Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space)..............................142
Figure 6.9 Access Sizes and Data Alignment Control (16-bit Access Space) ............................142
Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space ...........................................................144
Figure 6.11 Bus Timing for 8-Bit, 3-State Access Space ...........................................................145
Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access)...........146
Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) ............147
Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Word Access).................................148
Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access)...........149
Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) ............150
Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space (Word Access).................................151
Figure 6.18 Example of Wait State Insertion Timing .................................................................153
Figure 6.19 Example of Read Strobe Timing .............................................................................154
Figure 6.20 Example of Timing when Chip Select Assertion Period is Extended......................155
Figure 6.21 DRAM Basic Access Timing (RAST = 0, CAST = 0)............................................159
Figure 6.22 Example of Access Timing with 3-State Column Address Output Cycle
(RAST = 0) .............................................................................................................160
Figure 6.23 Example of Access Timing when RAS Signal Goes Low from Beginning
of T State (CAST = 0)............................................................................................161
r
Figure 6.24 Example of Timing with One Row Address Output Maintenance State
(RAST = 0, CAST = 0) ...........................................................................................162
Figure 6.25 Example of Timing with Two-State Precharge Cycle (RAST = 0, CAST = 0).......163
Figure 6.26 Example of Wait State Insertion Timing (2-State Column Address Output) ..........165
Figure 6.27 Example of Wait State Insertion Timing (3-State Column Address Output) ..........166
Figure 6.28 2-CAS Control Timing (Upper Byte Write Access: RAST = 0, CAST = 0) ..........167
Figure 6.29 Example of 2-CAS DRAM Connection ..................................................................168
Figure 6.30 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0) ...............................169
Figure 6.31 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1) ...............................170
Figure 6.32 Example of Operation Timing in RAS Down Mode (RAST = 0, CAST = 0).........171
Figure 6.33 Example of Operation Timing in RAS Up Mode (RAST = 0, CAST = 0)..............172
Figure 6.34 RTCNT Operation ...................................................................................................173
Figure 6.35 Compare Match Timing...........................................................................................173
Figure 6.36 CBR Refresh Timing ...............................................................................................174
Figure 6.37 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0).................174
Figure 6.38 Example of CBR Refresh Timing (CBRM = 1) ......................................................175
Figure 6.39 Self-Refresh Timing ................................................................................................176
Figure 6.40 Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States ...............................................................................................................177
Rev. 1.0, 09/01, page xxvi of xliv