Timer Synchronous Register (Tsyr) - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

11.3.9

Timer Synchronous Register (TSYR)

TSYR selects independent operation or synchronous operation for the TCNT counters of channels
0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Bit Bit Name
–
7
–
6
5 SYNC5
4 SYNC4
3 SYNC3
2 SYNC2
1 SYNC1
0 SYNC0
Rev. 1.0, 09/01, page 530 of 904
Initial value R/W
–
R/W
–
R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Reserved
These bits should always be written with 0.
Timer Synchronization 5 to 0
These bits select whether operation is independent of
or synchronized with other channels.
When synchronous operation is selected,
synchronous presetting of multiple channels, and
synchronous clearing through counter clearing on
another channel are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit, the
TCNT clearing source must also be set by means of
bits CCLR2 to CCLR0 in TCR.
0: TCNT_5 to TCNT_0 operates independently
(TCNT presetting /clearing is unrelated to
other channels)
1: TCNT_5 to TCNT_0 performs synchronous
operation (TCNT synchronous presetting/
synchronous clearing is possible)