Serial Control Register (Scr) - Hitachi H8/3032 Series Hardware Manual

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11.2.6 Serial Control Register (SCR)

SCR enables the SCI transmitter and receiver, enables or disables serial clock output in
asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source.
Bit 7
TIE RIE
Initial value 0
Read/Write R/W R/W
Receive interrupt enable
Enables or disables receive-data-full interrupts (RXI) and
receive-error interrupts (ERI)
Transmit interrupt enable
Enables or disables transmit-data-empty interrupts (TXI)
The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby
mode.
6 5 4 3
TE RE MPIE
0 0 0 0
R/W R/W R/W
Multiprocessor interrupt enable
Enables or disables multiprocessor
interrupts
Receive enable
Enables or disables the receiver
Transmit enable
Enables or disables the transmitter
321
2 1 0
TEIE CKE1 CKE0
0 0 0
R/W R/W R/W
Clock enable 1/0
These bits select the
SCI clock source
Transmit end interrupt enable
Enables or disables transmit-
end interrupts (TEI)