Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 273

Address bus
Precharge-sel
CKE
DQMU, DQML
Data bus
Figure 6.82 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
Write Accesses to Continuous Synchronous DRAM Space in RAS Down Mode
Continuous synchronous
DRAM space read
T T
p r
ø
Column Row
address address
PALL ACTV READ
(SDWCD = 1, CAS Latency 2)
Continuous synchronous
DRAM space write
T T T T
c1 cl c2 i
Column
External address
address
High
NOP
Idle cycle
Rev. 1.0, 09/01, page 229 of 904
T T
c1 c2
WRIT