Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 28

Figure 6.72 Example of Synchronous DRAM Full Access after External Read
(CAS Latency 2) ......................................................................................................219
Figure 6.73 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area)
(IDLC = 0, CAS Latency 2)....................................................................................220
Figure 6.74 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area)
(IDLC = 1, CAS Latency 2)....................................................................................221
Figure 6.75 Example of Idle Cycle Operation in RAS Down Mode (Write after Read)
(IDLC = 0, CAS Latency 2).....................................................................................222
Figure 6.76 Example of Idle Cycle Operation after DRAM Access (Consecutive Reads in
Different Areas) (IDLC = 0, RAST = 0, CAST = 0) ..............................................223
Figure 6.77 Example of Idle Cycle Operation after DRAM Access (Write after Read) (IDLC = 0,
RAST = 0, CAST = 0) ..........................................................................................................223
Figure 6.78 Example of Idle Cycle Operation after DRAM Write Access
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0)........................................................224
Figure 6.79 Example of Idle Cycle Operation after Continuous Synchronous DRAM
Space Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2)..225
Figure 6.80 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2) .....................226
Figure 6.81 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read
and Write Accesses to DRAM Space in RAS Down Mode.....................................228
Figure 6.82 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read
and Write Accesses to Continuous Synchronous DRAM Space in RAS
Down Mode (SDWCD = 1, CAS Latency 2)..........................................................229
Figure 6.83 Example of Timing when Write Data Buffer Function is Used...............................231
Figure 6.84 Bus Released State Transition Timing.....................................................................234
Figure 6.85 Bus Release State Transition Timing when Synchronous DRAM Interface ...........235
Section 7 DMA Controller (DMAC)
Figure 7.1 Block Diagram of DMAC .........................................................................................242
Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A) ...............................................267
Figure 7.3 Operation in Sequential Mode ...................................................................................274
Figure 7.4 Example of Sequential Mode Setting Procedure .......................................................275
Figure 7.5 Operation in Idle Mode .............................................................................................276
Figure 7.6 Example of Idle Mode Setting Procedure..................................................................277
Figure 7.7 Operation in Repeat mode .........................................................................................279
Figure 7.8 Example of Repeat Mode Setting Procedure.............................................................280
Figure 7.9 Operation in Single Address Mode (When Sequential Mode is Specified)...............282
Figure 7.10 Example of Single Address Mode Setting Procedure
(When Sequential Mode is Specified)......................................................................283
Figure 7.11 Operation in Normal Mode......................................................................................285
Figure 7.12 Example of Normal Mode Setting Procedure..........................................................286
Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0) .................................................288
Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1) .................................................289
Figure 7.15 Operation Flow in Block Transfer Mode.................................................................290
Rev. 1.0, 09/01, page xxviii of xliv