Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 829

Write pulse application subroutine
Write pulse application
Enable WDT
Set PSU bit in FLMCR1
Wait (y) µs
*6
Set P bit in FLMCR1
Wait (z1) µs or (z2) µs or (z3) µs
*5 *6
Clear P bit in FLMCR1
Wait (α) µs
Clear PSU bit in FLMCR1
Wait (β) µs
Disable WDT
End sub
Note 7: Write Pulse Width
Write Time (z) µs
Number of Writes (n)
1 z1
2 z1
3 z1
4 z1
5 z1
6 z1
7 z2
8 z2
9 z2
10 z2
11 z2
12 z2
13 z2
. .
. .
. .
998 z2
999 z2
1000 z2
Note: Use a z3 µs write pulse for additional
programming.
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Additional program data
storage area (128 bytes)
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must
be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (W) units.
3. The reprogram data is given by the operation of the following tables (comparison between stored data in the program data area and verify data).
Programming is executed for the bits of reprogram data 0 in the next reprogram loop. Even bits for which programming has been completed will
be subjected to additional programming if they fail the subsequent verify operation.
4. A 128-byte areas for storing program data, reprogram data, and additional program data must be provided in the RAM. The contents of the
reprogram and additional program data are modified as programming proceeds.
5. A write pulse of (z1) or (z2) µs should be applied according to the progress of the programming operation. See Note 7 for the pulse widths.
When writing of additional-programming data is executed, a (z3) µs write pulse should be applied.
Reprogram data X' means reprogram data when the write pulse is applied.
6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 24.6, Flash Memory Characteristics.
Program Data Operation Chart
Original Data (D)
Additional Program Data Operation Chart
Reprogram Data (X')
Figure 20.9 Program/Program-Verify Flowchart
Start of programming
Start
Set SWE bit in FLMCR1
Wait (x) µs
Store 128-byte program data in program
data area and reprogram data area
n = 1
m = 0
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Write pulse application
(z1) µs or (z2) µs
Set PV bit in FLMCR1
Wait (γ) µs
H'FF dummy write to verify address
Wait (ε) µs
Increment address
Read verify data
Write data = verify
data?
6 ≥ n ?
Additional program data computation
Transfer additional program data to
additional program data area
Reprogram data computation
Transfer reprogram data to reprogram
data area
128-byte
data verification
NG
completed?
Clear PV bit in FLMCR1
Wait (η) µs
6 ≥ n ?
Sequentially write 128-byte data in
additional program data area in RAM to
flash memory
Write pulse application
(z3) µs
(additional programming)
m = 0?
Clear SWE bit in FLMCR1
Wait (θ) µs
End of programming
Verify Data (V) Reprogram Data (X)
0 0 1
1 0
1 0 1
1
Verify Data (V) Additional Program Data (Y)
0 0 0
1 1
1 0
1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
*6
*4
*1
Sub-routine-call
See Note 7 for pulse width
*6
*2
NG
m = 1
OK
NG
OK
*4
*3
*4
OK
*6
NG
OK
*1
Sub-routine-call
*6
*6
NG
n ≥ (N)?
OK
OK
Clear SWE bit in FLMCR1
Wait (θ) µs
*6
Programming failure
Comments
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Comments
Additional programming executed
Additional programming not executed
Additional programming not executed
Additional programming not executed
Rev. 1.0, 09/01, page 785 of 904
n ← n + 1
NG
*6