Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 544

Bit Bit Name
7 CCLR2
6 CCLR1
5 CCLR0
4 CKEG1
3 CKEG0
2 TPSC2
1 TPSC1
0 TPSC0
Rev. 1.0, 09/01, page 500 of 904
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Counter Clear 2 to 0
These bits select the TCNT counter clearing source.
See tables 11.3 and 11.4 for details.
Clock Edge 1 and 0
These bits select the input clock edge. When the
input clock is counted using both edges, the input
clock period is halved (e.g. ø/4 both edges = ø/2
rising edge). If phase counting mode is used on
channels 1, 2, 4, and 5, this setting is ignored and the
phase counting mode setting has priority. Internal
clock edge selection is valid when the input clock is
ø/4 or slower. This setting is ignored if the input clock
is ø/1, or when overflow/underflow of another
channel is selected.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
Legend: x: Don't care
Time Prescaler 2 to 0
These bits select the TCNT counter clock. The clock
source can be selected independently for each
channel. See tables 11.5 to 11.10 for details.