Interrupt Exception Handling Sequence - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

Level 7 interrupt?
Mask level 6
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance
5.6.3

Interrupt Exception Handling Sequence

Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.
Rev. 1.0, 09/01, page 98 of 904
Program execution status
Interrupt generated?
Yes
No
Yes
Level 6 interrupt?
No
or below?
Yes
Save PC, CCR, and EXR
Update mask level
Read vector address
Branch to interrupt handling routine
in Interrupt Control Mode 2
No
Yes
NMI
No
No
Yes
No
Mask level 5
or below?
Yes
Clear T bit to 0
No
Level 1 interrupt?
Yes
No
Mask level 0?
Yes
Hold
pending