Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 267

T
p
ø
Address bus
,
Data bus
Figure 6.76 Example of Idle Cycle Operation after DRAM Access
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)
ø
Address bus
,
,
Data bus
Figure 6.77 Example of Idle Cycle Operation after DRAM Access
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)
DRAM space read External address space read
T T T T
r c1 c2
Idle cycle
DRAM space read
T T T T
p r c1 c2
Idle cycle
T T T
i 1 2 3
External address space write
T T T T
i 1 2 3
Rev. 1.0, 09/01, page 223 of 904
DRAM space read
T T T
i c1 c2
DRAM space read
T T
c1 c2