Breqo Output Timing; Notes On Usage Of The Synchronous Dram - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

%5(42 Output Timing %5(42
%5(42 %5(42
6.14.4
When the BREQOE bit is set to 1 and the %5(42 signal is output, %5(42 may go low before
the %$&. signal.
This will occur if the next external access request or CBR refresh request occurs while internal bus
arbitration is in progress after the chip samples a low level of %5(4.
6.14.5

Notes on Usage of the Synchronous DRAM

Setting of Synchronous DRAM Interface: The DCTL pin must be fixed to 1 to enable the
synchronous DRAM interface. Do not change the DCTL pin during operation.
Connection Clock: Be sure to set the clock to be connected to the synchronous DRAM to
SDRAMφ.
:$,7 Pin: In the continuous synchronous DRAM space, insertion of the wait state by the :$,7 :$,7
:$,7 :$,7
pin is disabled regardless of the setting of the WAITE bit in BCR.
Bank Control: This LSI cannot carry out the bank control of the synchronous DRAM. All banks
are selected.
Burst Access: The burst read/burst write mode of the synchronous DRAM is not supported.
When setting the mode register of the synchronous DRAM, set to the burst read/single write and
set the burst length to 1.
CAS Latency: When connecting a synchronous DRAM having CAS latency of 1, set the BE bit
to 0 in the DRAMCR.
Rev. 1.0, 09/01, page 239 of 904